1. Field of the Invention
The present invention relates to a technology for analyzing clock gating in large-scale integrated (LSI) semiconductor circuits.
2. Description of the Related Art
Clock gating (function) is a common technique for reducing power consumption of LSI circuits and involves terminating, as close as possible to the source, clock signals for an inactive portion of an LSI circuit to reduce power consumption resulting from the propagation of unnecessary clock signals. Conventionally, since clock gating was manually inserted in large blocks, designers could completely comprehend the operation of the clock gating function. Conventional clock gating verification includes timing verification of clock system signals, i.e., verifying whether the arrival timing of a control signal of individual clock gates falls within a range of normal operation, (see, for example, Japanese Patent Application Laid-Open Publication Nos. 8-202569 and 11-259554), and timing verification of data system signals with consideration of the clock gate function (see, for example, M. Kawarabayashi, et al., “A Verification Technique for Gated Clock”, Proceedings of the Design Automation Conference, pp. 123-127, 1993).
With regard to clock gating verification other than by timing verification, tools have been disclosed to the extent of extracting and depicting a partial circuit related to the clock gating (see, for example, Japanese Patent Application Laid-Open Publication No. 10-283381).
However, demand for further reductions in the power consumption of LSI circuits has increased and clock gating has been inserted in smaller blocks or automatically. The number of inserted clock gates has increased considerably, and overall comprehension of the relationships between individual clock gates has become nearly impossible for designers.
Under such circumstances, verification oversights of the clock gate function itself has become problematic. Specifically, if a clock is not terminated at a point where the clock must be terminated or if a clock is terminated at a point where the clock must not be terminated, this emerges as a function bug and, therefore, poor design due to the verification oversight becomes a problem. If a clock is not terminated at a point where the clock should be terminated, even when no function bug emerges, it is problematic in that electric power is wastefully consumed. Recently, strict limitations are placed on power consumption and a slight increase in consumption often becomes problematic as the target electric power is exceeded.